NCP1605DR2G【PDF 19/32 页】IC PFC CONTROLLER CCM/DCM 16SOIC

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Sheet目录45

15页 16页 17页 18页 [19页]20页 21页 22页 23页

NCP1605, NCP1605A, NCP1605B

http://onsemi.com

Figure 53. PFC Boost Converter

Figure 54. Inductor Current in DCM

out

Time

Inductor Current

The NCP1605 operates in voltage mode. As portrayed by

Figure 55, the MOSFET on time t

is controlled by the

signal V

ton

generated by the regulation block and the Pin

4 ramp as follows:

pin7

@ V

TON

pin7

(eq. 2)

The charge current that is sourced by Pin 7

pin7

= 60 mA/V

* (V

Pin4

)

] is constant at a given input

voltage (V

Pin4

is proportional to the output voltage). C

pin7

that is the capacitor connected between Pin 7 and ground

is also a constant. Hence, the power factor correction is

achieved when the V

TON

+ t

)/T term is constant.

The output of the regulation block (V

CONTROL

) is

linearly changed into a signal (V

REGUL

) varying between

0 and 1 V. (V

REGUL

) is the voltage that is injected into the

PWM section to modulate the MOSFET dutycycle.

However, like the NCP1601, the NCP1605 inserts some

circuitry that processes (V

REGUL

) to form the signal

TON

) that is used in the PWM section instead of

REGUL

) (see Figure 56). (V

TON

) is modulated in response

to the deadtime sensed during the precedent current

cycles, that is, for a proper shaping of the ac line current

(refer to NCP1601 data sheet). This modulation leads to:

TON

T @ V

REGUL

) t

or : V

TON

) t

+ V

REGUL

(eq. 3)

Given the regulation low bandwidth of the PFC systems,

CONTROL

) and then (V

REGUL

) are slow varying signals.

Hence, the (V

TON

* (t

+ t

)/T) term is substantially

constant. Provided that in addition, (t1) is proportional to

TON

), equation (1) leads to: (I

= k * V

), where k is a

constant. More exactly:

+ k @ V

(eq. 4)

where : k + constant +

pin7

@ V

REGUL

120 m @ L @ (V

pin2

)

The input current is then proportional to the input

voltage. Hence, the ac line current is properly shaped.

One can note that this analysis is also valid in the CRM

case. This condition is just a particular case of this

functioning where (t

= 0), which leads to (t

+ t

= T) and

TON

= V

REGUL

). That is why the NCP1605 automatically

adapts to the conditions and jumps from DCM and CRM

(and vice versa) without power factor degradation and

without discontinuity in the power delivery.

Remark: Like in the NCP1601, the V

TON

processing

circuit is informed when there is an OVP condition, not

to overdimension V

TON

in that conditions. Otherwise, an

OVP sequence would be viewed as a deadtime phase by

the circuit and V

TON

would inappropriately increase to

compensate it.

Similarly, the V

TON

processing circuit is inhibited for

a skip sequence not to overdimension V

TON

in this case

(refer to Figure 56).

Figure 55. PWM Circuit and Timing Diagram

Figure 56. V

TON

Processing Circuit

> Vton during (t1+t2)

> 0 V during t3 (deadtime)

> Vton*(t1+t2)/T in average

timing capacitor

sawtooth

to PWM latch

PWM

comparator

IN1

SKIP

OVP

OA1

OFF

(high during

deadtime)

The integrator OA1 amplifies the error between V

REGUL

and

IN1 so that in average, (V

TON

*(t1+t2)/T) equates V

REGUL

ton

Ramp Voltage

PWM Outtage

Turns Off MOSFET

ton

ramp

PWM Comparator

Closed When

Output Low

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